Layout design of D Flip Flop for Power and Area Reduction
نویسندگان
چکیده
Design of low power device is now an essential field of research due to increase in demand of portable devices. In this paper a single edge triggered D flip flop with low power and low area requirements is proposed. This D flip flop has been implemented using 180 nm technology. The layout of D FF is designed using fully automatic, semi custom layout and fully custom layout techniques. It can be observed from simulation result the fully custom design has shown 38% reduction in area and 35% reduction in power as compared to fully automatic design. The overall design area is optimized to enhance the chip density. It can be used in various applications like digital VLSI clocking, buffers, registers, microprocessors etc.
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